Difference between revisions of "Vlsi:Cadence Tips"

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(Fixing assura labprint.)
(Add warnings/errors to transient simulations)
 
(8 intermediate revisions by 2 users not shown)
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If you have two wires on a layout that are unconnected but will be connected together in a higher level then place a pin on both wires. When running Assura LVS you need to set some further options. Enable "View avParameters" and then click "Modify avParameters...". Find the "joinPins" option, enable it ("Use in run") and set it to "Top". Click OK to close the avParameters window. Now enable "View Additional Functions" followed by "Use joinableNet Function". Now click "Modify joinableNet Function...". In the new window enable "root cell?" then add your net to the "Net Names to Join" box and click "Add to Command List (below)" to add it. Click OK to close the joinableNet window and then run LVS as normal.
 
If you have two wires on a layout that are unconnected but will be connected together in a higher level then place a pin on both wires. When running Assura LVS you need to set some further options. Enable "View avParameters" and then click "Modify avParameters...". Find the "joinPins" option, enable it ("Use in run") and set it to "Top". Click OK to close the avParameters window. Now enable "View Additional Functions" followed by "Use joinableNet Function". Now click "Modify joinableNet Function...". In the new window enable "root cell?" then add your net to the "Net Names to Join" box and click "Add to Command List (below)" to add it. Click OK to close the joinableNet window and then run LVS as normal.
  
=== Fixing Voltage Storm (for an admin to do) ===
+
=== Voltage / Current Pulse Sources ===
  
Replace $CDSDIR/tools/sev/bin/vsa2 with:
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I can never remember which voltage/current is which, so I've created an image to remind me: [[Image:Vpulse.png]]
  
#!/bin/ksh
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== RC Extraction for C35/S35/H35 in IC 6.1 ==
 
export LD_LIBRARY_PATH=/eee/vlsi/Cadence/2006/IC/tools/dfII/lib:/eee/vlsi/Cadence/2006/IC/tools/lib
 
/eee/vlsi/Cadence/2006/IC/tools/sev/bin/32bit/vsa2 $*
 
  
Install libtermcap.
+
To run RCX successfully, you must first pass LVS correctly as normal. Do this by running LVS without any switches. If you run RCX now, it will fail. Now carry out LVS with the switch "resimulate_extracted" to guarantee that also substrate shorts are found correctly. RCX will run without any problems (note that you must not use the "resimulate_extracted" switch for normal LVS runs as it may give false results.
  
zypper install termcap termcap-32bit
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== Add warnings/errors to transient/dc simulations ==
  
=== Fixing Assura label printing (for an admin to do) ===
+
From http://www.cadence.com/Community/forums/p/14258/23865.aspx
 +
in the ADE gui you can use the "Simulation -> Device Checking"  interface.  It will create "assert" statements in your netlist
 +
 +
(See "spectre -help assert" ).
 +
 +
Here an example where I check a node voltage of a resistor if it exceeds a volatage range with a time limit:
 +
 +
Check_net assert expr="(V(R0:1) )" min=1 max=2 duration=1u message="Voltage Exceeds Maximum" level=warning
 +
 +
"Check_net" is just a name. "level" can be also "error" which will stop the simulation.
  
If you specify nets to be extracted or want to have power supply nets labelled during extraction, Assura will use labprint which has glibc issues. To get around this problem, copy $ASSURADIR/tools/assura/bin/64bit/labprint to $ASSURADIR/tools/assura/bin/32bit/labprint and $ASSURADIR/tools/assura/bin/labprint. This only works for 64 bit machines obviously, but I've not found a solution that will allow 32 bit labprint to run.
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A better description:
 +
 
 +
To enable device checking, use the menu Simulation->Options->Analog
 +
Look in the "Check" tab and add a tick to the checkbox "dochecklimit" under "DEVICE CHECKING OPTIONS".
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Click OK.
 +
 +
Now go to the menu Simulation->Device Checking...
 +
A very simple check is to look at the voltage on a net. For more options like checking device parameters,
 +
click "Help" in the Device Check Specification window.
 +
Choose "Type" as "Expression", then type your expression in. This would be "V(out)" to check the voltage on
 +
a net named "out". Set the min/max range for your check and click "Add".
 +
Now run a simulation and check the output log.

Latest revision as of 10:43, 14 December 2009

Virtual Connections in Assura LVS

If you have two wires on a layout that are unconnected but will be connected together in a higher level then place a pin on both wires. When running Assura LVS you need to set some further options. Enable "View avParameters" and then click "Modify avParameters...". Find the "joinPins" option, enable it ("Use in run") and set it to "Top". Click OK to close the avParameters window. Now enable "View Additional Functions" followed by "Use joinableNet Function". Now click "Modify joinableNet Function...". In the new window enable "root cell?" then add your net to the "Net Names to Join" box and click "Add to Command List (below)" to add it. Click OK to close the joinableNet window and then run LVS as normal.

Voltage / Current Pulse Sources

I can never remember which voltage/current is which, so I've created an image to remind me: Vpulse.png

RC Extraction for C35/S35/H35 in IC 6.1

To run RCX successfully, you must first pass LVS correctly as normal. Do this by running LVS without any switches. If you run RCX now, it will fail. Now carry out LVS with the switch "resimulate_extracted" to guarantee that also substrate shorts are found correctly. RCX will run without any problems (note that you must not use the "resimulate_extracted" switch for normal LVS runs as it may give false results.

Add warnings/errors to transient/dc simulations

From http://www.cadence.com/Community/forums/p/14258/23865.aspx

in the ADE gui you can use the "Simulation -> Device Checking"   interface.  It will create "assert" statements in your netlist

(See "spectre -help assert" ).

Here an example where I check a node voltage of a resistor if it exceeds a volatage range with a time limit:

Check_net assert expr="(V(R0:1) )" min=1 max=2 duration=1u message="Voltage Exceeds Maximum" level=warning

"Check_net" is just a name. "level" can be also "error" which will stop the simulation.

A better description:

To enable device checking, use the menu Simulation->Options->Analog
Look in the "Check" tab and add a tick to the checkbox "dochecklimit" under "DEVICE CHECKING OPTIONS".
Click OK.

Now go to the menu Simulation->Device Checking...
A very simple check is to look at the voltage on a net. For more options like checking device parameters,
click "Help" in the Device Check Specification window.
Choose "Type" as "Expression", then type your expression in. This would be "V(out)" to check the voltage on
a net named "out". Set the min/max range for your check and click "Add".
Now run a simulation and check the output log.