Vlsi:Cadence PCells

Introduction

This guide aims to describe how to make parameterised layout cells (pells) in Cadence. Pcells are layouts with parameters that can be modified and the layout will be updated automatically. FETs are usually implemented as pcells so that the width, length, presence of substrate contact and other parameters can be easily changed.

As it stands, this is just a document describing how to make an address decoder element using pcells and so does not describe all of the available pcell features. For more information on pcells, consult the Cadence documentation on pcells which is actually is very good. It can be found at: $CDSDIR/IC/doc/pcellref/pcellref.pdf

Pcell Example: 2 to 4 Address Decoder

3.1 Introduction An address decoder is a perfect example of where using a pcell makes perfect sense. The decoder is made up of nearly identical elements, the only difference being whether the inputs are inverted or not. Furthermore, for large decoders, the chance of human error is quite high when making them manually. Using a pcell reduces the chance of an error.

This example explains how to use the “Conditional Inclusion” feature to create an address decoder element.

Schematic Design

Figure 1 shows the schematic of our two bit decoder element. The choice of which address is selected is determined in the full decoder schematic by having inverted or non-inverted inputs to each element, as shown in figure 2.

Figure 1: 2 to 4 Address Decoder Element Schematic

In the layout, the inverters will appear (or not) in the element cell and the full decoder will consist of tiled elements.

Layout

For simplicity, the layouts only show the metal layers.

In the layout, we want to have a design that takes our address inputs to the inputs of a NOR23 but that can also take our address inputs through an inverter before being fed into the NOR23.

A simple way of doing this is to overlay the cells and wiring for both cases in the same layout. We can then choose which of them to display by using the pcell“Conditional Inclusion” feature.

Figure 2: 2 to 4 Address Decoder Schematic

Step 1

Create the layout as shown in figure 3. The FILL2 cells are placeholders for the INV0 cells that will be optionally added to invert the inputs. This is the non-inverted case and is defined as having A0=true and A1=true, where A0 and A1 are our address parameters as passed to the pcell.

Figure 3: Non-Inverted Decoder Layout

Step 2

Now move the FILL2 cells up out of the way and add INV0 cells in their place. You need to modify the wiring so that the address inputs A<0> and A<1> are connected to the inputs of the inverters and the outputs of the inverters are connected to the NOR23 inputs, but without deleting the existing wiring. This results in something like figure 4 (the FILL2 cells have been removed from this figure).

Step 3

This is the tricky bit. What we want is to change the wiring again so that the inverted and the noninverted case can be used independently of one another. For the wiring we have added so far, there are three possibilities. It is either common to both the inverted and the non-inverted case, is only for the inverted case or is only for the non-inverted case. At the moment, some of the wiring that is a single path is used in two of those cases, so the path must be split. The easiest way to split a path in this case is to draw two new paths over the top of the existing path and then delete the old path. The result is shown in figure 5. The splits are in the MET2 paths (yellow) and are circled to make them more obvious.

Step 4

We now need to set parts of the layout to be included or not based on our parameters. Considering the A<1> wiring, the MET3 path (green) should always be there, as should the VIA2. The left most piece of MET2 should also always be there. If we are in the inverting case (A1 parameter

Figure 4: Inverted Decoder Layout Figure 5: Split Paths Layout

set to false), the vertical MET2 should be shown, as should the VIA1, the INV0 as well as the MET2 from the output of the INV0 to the input of the NOR23. If we are in the non-inverting case, the right most piece of MET2 should be shown, as should the FILL2 cell. All other parts should be invisible. To put the layout into pcell mode, go to the menu Tools->Pcell. A Pcell menu will appear on the right of the window. Select the FILL2 cell which will be placed over the INV0 for A<1>, as well as the right most piece of MET2 (from the split path) for A<1>. Now go to the menu Pcell->Conditional Inclusion->Define... A window will appear asking for an expression. You should enter“A1”, meaning that if a1 is true then your selection will be included. Now select the INV0 for A<1>, as well as the associated VIA1 cells and the output MET2. Define a new conditional inclusion, but this time set the expression as “A1 == nil”. This will include the selection if a1 is false. Repeat the above steps for A<0>, using A0 as the parameter name. To finish, move the FILL2 cells so they are exactly over the INV0 cells. Now select the menu Pcell- >Compile->To Pcell and then save the layout.

Step 5

Create a new layout cell and check that both of the different parameters work as you expect!

Full Decoder

There are address decoder schematics available in the address decoders library. Use them to save yourself time - just modify the address* decoder element pcell schematic to fit your design and then create your pcell layout in the same cell. The full decoder schematics are in the address* decoder cells. To get the full layout, add an instance of the address* decoder spcell (spcell is a Skill pcell, that is to say a pcell created using the Skill programming language in Cadence) layout to your address* decoder layout to automatically generate the full decoder. You will need to tell the address* decoder spcell cell which cell it should use as an element and what its pitch is.