Difference between revisions of "Spartan Starter Pinouts"
From Applied Optics Wiki
(→A1 Connector: -> Using SRAM IO pins.) |
(→B1 Connector) |
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| Line 93: | Line 93: | ||
== B1 Connector == | == B1 Connector == | ||
| + | The pins marked in orange are used when the FPGA is being configured in slave parallel mode. | ||
{| border="1" cellpadding="2" | {| border="1" cellpadding="2" | ||
! FPGA Pin !! Connector !! Connector !! FPGA Pin | ! FPGA Pin !! Connector !! Connector !! FPGA Pin | ||
| Line 100: | Line 101: | ||
|style="background: red"| Vcco (+3.3V) ||style="background: red"| 3 || 4 || C10 | |style="background: red"| Vcco (+3.3V) ||style="background: red"| 3 || 4 || C10 | ||
|- | |- | ||
| − | | T3 || 5 || 6 || E10 | + | |style="background: orange"| T3 ||style="background: orange"| 5 || 6 || E10 |
|- | |- | ||
| − | | N11 || 7 || 8 || C11 | + | |style="background: orange"| N11 ||style="background: orange"| 7 || 8 || C11 |
|- | |- | ||
| − | | P10 || 9 || 10 || D11 | + | |style="background: orange"| P10 ||style="background: orange"| 9 || 10 || D11 |
|- | |- | ||
| − | | R10 || 11 || 12 || C12 | + | |style="background: orange"| R10 ||style="background: orange"| 11 || 12 || C12 |
|- | |- | ||
| − | | T7 || 13 || 14 || D12 | + | |style="background: orange"| T7 ||style="background: orange"| 13 || 14 || D12 |
|- | |- | ||
| − | | R7 || 15 || 16 || E11 | + | |style="background: orange"| R7 ||style="background: orange"| 15 || 16 || E11 |
|- | |- | ||
| − | | N6 || 17 || 18 || B16 | + | |style="background: orange"| N6 ||style="background: orange"| 17 || 18 || B16 |
|- | |- | ||
| − | | M6 || 19 || 20 || R3 | + | |style="background: orange"| M6 ||style="background: orange"| 19 ||style="background: orange"| 20 ||style="background: orange"| R3 |
|- | |- | ||
| C15 || 21 || 22 || C16 | | C15 || 21 || 22 || C16 | ||
Revision as of 14:40, 16 March 2009
This page lists the pinouts of the expansion connectors on the Spartan 3 starter board. It also lists pins that can be used interchangably between connectors.
A1 Connector
The pins marked in orange are connected to the SRAM IO pins. To use them, the SRAM chip enable lines should be driven high. These are pins P7 and N5, which are not on the A1 connector.
| FPGA Pin | Connector | Connector | FPGA Pin |
|---|---|---|---|
| GND | 1 | 2 | VU (+5V) |
| Vcco (+3.3V) | 3 | 4 | N8 |
| N7 | 5 | 6 | L5 |
| T8 | 7 | 8 | N3 |
| R6 | 9 | 10 | M4 |
| T5 | 11 | 12 | M3 |
| R5 | 13 | 14 | L4 |
| C2 | 15 | 16 | G3 |
| C1 | 17 | 18 | K4 |
| B1 | 19 | 20 | P9 |
| M7 | 21 | 22 | M10 |
| F3 | 23 | 24 | A5 |
| E3 | 25 | 26 | A7 |
| G5 | 27 | 28 | A9 |
| H4 | 29 | 30 | A11 |
| J3 | 31 | 32 | A13 |
| K5 | 33 | 34 | K3 |
| L3 | 35 | 36 | JTAG Isolation |
| C13 | 37 | 38 | C14 |
| JTAG TDO | 39 | 40 | Header J7, pin 3 |
A2 Connector
| FPGA Pin | Connector | Connector | FPGA Pin |
|---|---|---|---|
| GND | 1 | 2 | VU (+5V) |
| Vcco (+3.3V) | 3 | 4 | E6 |
| D5 | 5 | 6 | C5 |
| D6 | 7 | 8 | C6 |
| E7 | 9 | 10 | C7 |
| D7 | 11 | 12 | C8 |
| D8 | 13 | 14 | C9 |
| D10 | 15 | 16 | A3 |
| B4 | 17 | 18 | A4 |
| B5 | 19 | 20 | A5 |
| B6 | 21 | 22 | B7 |
| A7 | 23 | 24 | B8 |
| A8 | 25 | 26 | A9 |
| B10 | 27 | 28 | A10 |
| B11 | 29 | 30 | B12 |
| A12 | 31 | 32 | B13 |
| A13 | 33 | 34 | B14 |
| D9 | 35 | 36 | B3 |
| R14 | 37 | 38 | N9 |
| T15 | 39 | 40 | M11 |
B1 Connector
The pins marked in orange are used when the FPGA is being configured in slave parallel mode.
| FPGA Pin | Connector | Connector | FPGA Pin |
|---|---|---|---|
| GND | 1 | 2 | VU (+5V) |
| Vcco (+3.3V) | 3 | 4 | C10 |
| T3 | 5 | 6 | E10 |
| N11 | 7 | 8 | C11 |
| P10 | 9 | 10 | D11 |
| R10 | 11 | 12 | C12 |
| T7 | 13 | 14 | D12 |
| R7 | 15 | 16 | E11 |
| N6 | 17 | 18 | B16 |
| M6 | 19 | 20 | R3 |
| C15 | 21 | 22 | C16 |
| D15 | 23 | 24 | D16 |
| E15 | 25 | 26 | E16 |
| F15 | 27 | 28 | G15 |
| G16 | 29 | 30 | H15 |
| H16 | 31 | 32 | J16 |
| K16 | 33 | 34 | K15 |
| L15 | 35 | 36 | B3 |
| R14 | 37 | 38 | N9 |
| T15 | 39 | 40 | M11 |
