Difference between revisions of "Spartan Starter Pinouts"

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This page lists the pinouts of the expansion connectors on the Spartan 3 starter board. It also lists pins that can be used interchangably between connectors.
+
This page lists the pinouts of the expansion connectors on the Spartan 3 starter board. It is intended as a quick reference to show which pins are available to use on all of the connectors interchangably. It does not replace the Xilinx user guide at http://www.xilinx.com/support/documentation/boards_and_kits/ug130.pdf
  
 
== A1 Connector ==
 
== A1 Connector ==
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{| border="1" style="text-align: center"
+
The pins marked in orange are connected to the SRAM IO pins. To use them, the SRAM chip enable lines should be driven high. These are pins P7 and N5, which are not on the A1 connector.
 +
{| class="wikitable" style="margin: 1em auto 1em auto; text-align: center"
 +
 
 
! FPGA Pin !! Connector !! Connector !! FPGA Pin
 
! FPGA Pin !! Connector !! Connector !! FPGA Pin
 
|-
 
|-
Line 27: Line 29:
 
| M7 || 21 || 22 || M10
 
| M7 || 21 || 22 || M10
 
|-
 
|-
−
| F3 || 23 || 24 || A5
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| F3 || 23 || 24 || G4
 
|-
 
|-
−
| E3 || 25 || 26 || A7
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| E3 || 25 || 26 || F4
 
|-
 
|-
−
| G5 || 27 || 28 || A9
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| G5 || 27 || 28 || E4
 
|-
 
|-
−
| H4 || 29 || 30 || A11
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| H4 || 29 || 30 || H3
 
|-
 
|-
−
| J3 || 31 || 32 || A13
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| J3 || 31 || 32 || J4
 
|-
 
|-
 
| K5 || 33 || 34 || K3
 
| K5 || 33 || 34 || K3
Line 46: Line 48:
 
|}
 
|}
  
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== B1 Connector ==
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== A2 Connector ==
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{| border="1" cellpadding="2"
+
{| class="wikitable" style="margin: 1em auto 1em auto; text-align: center"
 
! FPGA Pin !! Connector !! Connector !! FPGA Pin
 
! FPGA Pin !! Connector !! Connector !! FPGA Pin
 
|-
 
|-
−
! GND || 1 || 2 || VU (+5V)
+
|style="background: red"| GND ||style="background: red"| 1 ||style="background: red"| 2 ||style="background: red"| VU (+5V)
 
|-
 
|-
−
! Vcco (+3.3V) || 3 || 4 || N8
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|style="background: red"| Vcco (+3.3V) ||style="background: red"| 3 || 4 || E6
 
|-
 
|-
−
!  || 3 || 4 ||  
+
| D5 || 5 || 6 || C5
 
|-
 
|-
−
!  || 5 || 6 ||  
+
| D6 || 7 || 8 || C6
 
|-
 
|-
−
!  || 7 || 8 ||  
+
| E7 || 9 || 10 || C7
 
|-
 
|-
−
!  || 9 || 10 ||  
+
| D7 || 11 || 12 || C8
 
|-
 
|-
−
!  || 11 || 12 ||  
+
| D8 || 13 || 14 || C9
 
|-
 
|-
−
!  || 13 || 14 ||  
+
| D10 || 15 || 16 || A3
 
|-
 
|-
−
!  || 15 || 16 ||  
+
| B4 || 17 || 18 || A4
 
|-
 
|-
−
!  || 17 || 18 ||  
+
| B5 || 19 || 20 || A5
 
|-
 
|-
−
!  || 19 || 20 ||  
+
| B6 || 21 || 22 || B7
 
|-
 
|-
−
!  || 21 || 22 ||  
+
| A7 || 23 || 24 || B8
 
|-
 
|-
−
!  || 23 || 24 ||  
+
| A8 || 25 || 26 || A9
 
|-
 
|-
−
!  || 25 || 26 ||  
+
| B10 || 27 || 28 || A10
 
|-
 
|-
−
!  || 27 || 28 ||  
+
| B11 || 29 || 30 || B12
 
|-
 
|-
−
!  || 29 || 30 ||  
+
| A12 || 31 || 32 || B13
 
|-
 
|-
−
!  || 31 || 32 ||  
+
| A13 || 33 || 34 || B14
 
|-
 
|-
−
!  || 33 || 34 ||  
+
| D9 || 35 ||style="background: red"| 36 ||style="background: red"| B3
 
|-
 
|-
−
!  || 35 || 36 ||  
+
|style="background: red"| R14 ||style="background: red"| 37 ||style="background: red"| 38 ||style="background: red"| N9
 
|-
 
|-
−
!  || 37 || 38 ||  
+
|style="background: red"| T15 ||style="background: red"| 39 ||style="background: red"| 40 ||style="background: red"| M11
−
|-
 
−
!  || 39 || 40 ||  
 
 
|}
 
|}
  
−
== B2 Connector ==
+
== B1 Connector ==
−
{| border="1" cellpadding="2"
+
The pins marked in orange are used when the FPGA is being configured in slave parallel mode.
 +
{| class="wikitable" style="margin: 1em auto 1em auto; text-align: center"
 
! FPGA Pin !! Connector !! Connector !! FPGA Pin
 
! FPGA Pin !! Connector !! Connector !! FPGA Pin
 
|-
 
|-
−
! GND || 1 || 2 || VU (+5V)
+
|style="background: red"| GND ||style="background: red"| 1 ||style="background: red"| 2 ||style="background: red"| VU (+5V)
−
|-
 
−
! Vcco (+3.3V) || 3 || 4 || N8
 
 
|-
 
|-
−
!  || 3 || 4 ||  
+
|style="background: red"| Vcco (+3.3V) ||style="background: red"| 3 || 4 || C10
 
|-
 
|-
−
!  || 5 || 6 ||  
+
|style="background: orange"| T3 ||style="background: orange"| 5 || 6 || E10
 
|-
 
|-
−
!  || 7 || 8 ||  
+
|style="background: orange"| N11 ||style="background: orange"| 7 || 8 || C11
 
|-
 
|-
−
!  || 9 || 10 ||  
+
|style="background: orange"| P10 ||style="background: orange"| 9 || 10 || D11
 
|-
 
|-
−
!  || 11 || 12 ||  
+
|style="background: orange"| R10 ||style="background: orange"| 11 || 12 || C12
 
|-
 
|-
−
!  || 13 || 14 ||  
+
|style="background: orange"| T7 ||style="background: orange"| 13 || 14 || D12
 
|-
 
|-
−
!  || 15 || 16 ||  
+
|style="background: orange"| R7 ||style="background: orange"| 15 || 16 || E11
 
|-
 
|-
−
!  || 17 || 18 ||  
+
|style="background: orange"| N6 ||style="background: orange"| 17 || 18 || B16
 
|-
 
|-
−
!  || 19 || 20 ||  
+
|style="background: orange"| M6 ||style="background: orange"| 19 ||style="background: orange"| 20 ||style="background: orange"| R3
 
|-
 
|-
−
!  || 21 || 22 ||  
+
| C15 || 21 || 22 || C16
 
|-
 
|-
−
!  || 23 || 24 ||  
+
| D15 || 23 || 24 || D16
 
|-
 
|-
−
!  || 25 || 26 ||  
+
| E15 || 25 || 26 || E16
 
|-
 
|-
−
!  || 27 || 28 ||  
+
| F15 || 27 || 28 || G15
 
|-
 
|-
−
!  || 29 || 30 ||  
+
| G16 || 29 || 30 || H15
 
|-
 
|-
−
!  || 31 || 32 ||  
+
| H16 || 31 || 32 || J16
 
|-
 
|-
−
!  || 33 || 34 ||  
+
| K16 || 33 || 34 || K15
 
|-
 
|-
−
!  || 35 || 36 ||  
+
| L15 || 35 ||style="background: red"| 36 ||style="background: red"| B3
 
|-
 
|-
−
!  || 37 || 38 ||  
+
|style="background: red"| R14 ||style="background: red"| 37 ||style="background: red"| 38 ||style="background: red"| N9
 
|-
 
|-
−
!  || 39 || 40 ||  
+
|style="background: red"| T15 ||style="background: red"| 39 ||style="background: red"| 40 ||style="background: red"| M11
 
|}
 
|}

Latest revision as of 16:41, 25 November 2009

This page lists the pinouts of the expansion connectors on the Spartan 3 starter board. It is intended as a quick reference to show which pins are available to use on all of the connectors interchangably. It does not replace the Xilinx user guide at http://www.xilinx.com/support/documentation/boards_and_kits/ug130.pdf

A1 Connector

The pins marked in orange are connected to the SRAM IO pins. To use them, the SRAM chip enable lines should be driven high. These are pins P7 and N5, which are not on the A1 connector.

FPGA Pin Connector Connector FPGA Pin
GND 1 2 VU (+5V)
Vcco (+3.3V) 3 4 N8
N7 5 6 L5
T8 7 8 N3
R6 9 10 M4
T5 11 12 M3
R5 13 14 L4
C2 15 16 G3
C1 17 18 K4
B1 19 20 P9
M7 21 22 M10
F3 23 24 G4
E3 25 26 F4
G5 27 28 E4
H4 29 30 H3
J3 31 32 J4
K5 33 34 K3
L3 35 36 JTAG Isolation
C13 37 38 C14
JTAG TDO 39 40 Header J7, pin 3

A2 Connector

FPGA Pin Connector Connector FPGA Pin
GND 1 2 VU (+5V)
Vcco (+3.3V) 3 4 E6
D5 5 6 C5
D6 7 8 C6
E7 9 10 C7
D7 11 12 C8
D8 13 14 C9
D10 15 16 A3
B4 17 18 A4
B5 19 20 A5
B6 21 22 B7
A7 23 24 B8
A8 25 26 A9
B10 27 28 A10
B11 29 30 B12
A12 31 32 B13
A13 33 34 B14
D9 35 36 B3
R14 37 38 N9
T15 39 40 M11

B1 Connector

The pins marked in orange are used when the FPGA is being configured in slave parallel mode.

FPGA Pin Connector Connector FPGA Pin
GND 1 2 VU (+5V)
Vcco (+3.3V) 3 4 C10
T3 5 6 E10
N11 7 8 C11
P10 9 10 D11
R10 11 12 C12
T7 13 14 D12
R7 15 16 E11
N6 17 18 B16
M6 19 20 R3
C15 21 22 C16
D15 23 24 D16
E15 25 26 E16
F15 27 28 G15
G16 29 30 H15
H16 31 32 J16
K16 33 34 K15
L15 35 36 B3
R14 37 38 N9
T15 39 40 M11
Retrieved from "http://optics.eee.nottingham.ac.uk/w/index.php?title=Spartan_Starter_Pinouts&oldid=541"