Difference between revisions of "VLSI"
From Applied Optics Wiki
(Configuring jtag cables for Xilinx ISE.) |
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* [http://www.xilinx.com/support/documentation/application_notes/xapp623.pdf Xilinx PCB decoupling guide] | * [http://www.xilinx.com/support/documentation/application_notes/xapp623.pdf Xilinx PCB decoupling guide] | ||
* [[Vlsi:VHDL_Links|VHDL Links]] | * [[Vlsi:VHDL_Links|VHDL Links]] | ||
| − | + | * [[AMS Design Kits]] | |
== Clear a Cable Lock in Impact == | == Clear a Cable Lock in Impact == | ||
Latest revision as of 14:13, 30 October 2008
Pages of interest for members of the VLSI group:
- Component Suppliers
- Semiconductor Manufacturers
- Cadence Tips
- Xilinx PCB decoupling guide
- VHDL Links
- AMS Design Kits
Clear a Cable Lock in Impact
impact -batch setmode -bs cleancablelock setcable -p auto quit
Configuring JTAG Cables
For parallel port cables, add the following to /etc/init.d/boot.local:
modprobe ppdev chmod a+rw /dev/parport0
For Xilinx USB cables, install fxload and the rest should be automatic.
