Difference between revisions of "CMOS Digital Design"

Revision as of 17:36, 19 November 2013

This is a quick flow for digital IC design flow.

Please borrow the MSC/STFC Introduction to Digital IC Design Flows from Roger Light (x13233).

Platform: Cadence/Incisive/RTL Compiler/AMS C35

1. VHDL to RTL
   1. Write and test your VHDL code. You can do this with Xilinx or in any text editor. If you use a text editor you can simulate your code using NCLab.
   2. Create a folder for the RTL compiler
   3. Copy the relevant vhdl/verilog files into the folder
   4. Run rc at command prompt in the folder. This will generate a subfolder that RC uses to keep track of your design
   5. At the rc prompt point to the correct process library setting attributes with: set_attribute library /eee/vlsi/DesignKits/AMS/v4.00/liberty/c35_3.3V/c35_CORELIB.lib
   6. Read in your hdl using read_hdl -vhdl filename.vhd
   7. To actually make sense of the design structure, elaborate your design. This converts the VHDL to an in-memory netlist. Type elaborate
   8. Verify the design with check_design -all
   9. View the resulting RTL schematic by typing gui_show, then gui_raise to move GUI window above. Use gui_sync to keep prompt and GUI window synchronised.
   10. You can now synthesize your vhdl to a netlist that uses cells from your chosen library. Run synthesize. Run it 3 times to optimise
   11. Write your netlist to hdl as write_hdl > output.v
   12. Exit rc by typing rc.
2. RTL to layout
   1. Run ams_encounter -tech c35b4 (generates required library files)
   2. Run encounter at the command prompt. This starts encounter for layout planning, power planning
3. Choose File >> Import Design >> Load >> c35b4_std.conf
   1. Choose the veriloga file you've just exported
   2. Specify top or choose auto
   3. Save the design
   4. Now you can go through these steps to layout
      1. Floorplanning
         1. Floorplan >> Specify Floorplan
         2. Specify a width to length ratio. Aim for a utilization of 1. A good starting value is 0.8
      2. Power
         1. Add a ring around your core
         2. Power >> Power Planning >> Add ring
         3. The power rings we want are gnd! and vdd!.
         4. Click ... to choose nets (pulled from netlist)
         5. Specify layers and width/spacing
         6. Add stripes to connect the rings and distribute the power more evenly
         7. Save design
      3. Place end capacitors
         1. First place end-caps. These are fill cells that act as power decoupling/bypass capacitors.
         2. Do Place >> Physical Cell >> End Cap (R/L)
         3. Save design
      4. Edit pins
         1. Click Edit >> Pin editor on the menubar
         2. This allows you to determine the layout of the pins. You can specify which side of the silicon block to put pins, spacing, metal layer etc.
         3. Click apply after each edit to save and update positions
         4. Save the design
      5. Place design
         1. Place >> Place >> Standard Cell
         2. This places your design in the floorplan
         3. Switch to Physical View (on top right of tooolbar) to view the design
         4. Save the design
      6. Save SDF/SDC data
         1. Do Timing >> Extract RC
         2. Specify a filename and save to file.
      7. Route Power
         1. Choose Route >> Special Route
         2. This connects the power supply to your cells
      8. Route design
         1. Click Route >> Nano Route >>> Route
         2. It is a good idea to specify which metal layers should be used. We usually use Metals 1 to 3 with the C35 process. Specify this in the Routing Control, bottom:top layers section
         3. Save design
      9. Export the design
         1. The layout is complete now, and you can export it to GDS2.
         2. Click File>>Save>>GDS/Oasis
         3. Make sure to load gds.map
         4. Save as filename.gds
   5. Layout into Cadence
      1. Start Cadence
      2. From the IFCB choose File >> Import >> Stream