Difference between revisions of "Vlsi:Cadence Tips"

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(Added diagrams to Voltage Storm analysis procedure.)
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=== Tips with their own pages ===
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[[Vlsi:Cadence_Voltage_Storm]]
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=== Virtual Connections in Assura LVS ===
 
=== Virtual Connections in Assura LVS ===
  
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I can never remember which voltage/current is which, so I've created an image to remind me: [[Image:Vpulse.png]]
 
I can never remember which voltage/current is which, so I've created an image to remind me: [[Image:Vpulse.png]]
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=== Voltage Storm Analysis ===
 
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Voltage Storm is a tool that allows the analysis of IR drops. For example, it can be used to monitor the distribution of VDD across an array of pixels.
 
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Follow this procedure for the analysis:
 
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* Create your schematic and layout.
 
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* Make sure your labels are in the center of any path or metal or poly they are on.
 
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* From the '''Create''' menu, choose '''Pins from labels...''' and click OK to create pins on the layout.
 
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* Run LVS from Assura, and then run RCX to generate the extracted view. You may need to use the JoinableNet function if you haven't joined some nets together.
 
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* In the RCX window, choose to extract RC and use '''infinite Max Fracture Lengths squares''' in the Extraction tab, and enable '''extract parasitic resistor width''' (Netlisting Tab).
 
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* Set up a test bench configuration, containing the extracted view. Use the hierarchy editor.
 
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* Run a simulation that uses the extracted view. A short transient, AC or DC simulation is fine.
 
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* From your Spectre ADE window, choose '''Session >> Schematic Window''' to open the test cell, and descend into the extracted view. This makes sure that you are in context.
 
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* From the extracted view menu, choose '''Tools >> Voltage Storm''' from the menu.
 
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* Select from the '''EM and IR''' menu, '''IR Drop Analysis'''
 
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* Accept the use of the presistor (default)
 
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* If all was correctly set up, your pins and available signals will be listed. Select the pins or signals of interest, using the '''CTRL''' key for multiple selections.
 
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* Enter or browse to your simulation directory.
 
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* Highlight one of the simulations in the list box.
 
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* Press OK. The tool will perform some operations (can be seen in the CIW), and an '''IR Voltage Drop Results''' window will pop up.
 
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* This allows you to choose on of those pins/signals chosen earlier, and study the drop.
 
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* To display the voltage distribution, click one of the buttons near the bottom of the form. '''Hide layers, Display highlights''' is particularly useful.
 
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* It may be necessary to load a resource file in your LSW to get the layers to display in a nice format. From the LSW, choose '''Edit >> Resource Editor''', and from that window choose '''File >> Load'''
 
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* The voltage variation is shown in the form of a colour map on the extracted layout window.
 
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[[Image:MLCv6VDDirDrop8pin.png|300px|VDD Distribution shown on colour map]]  [[Image:MLCv6VDDirDrop8pinlegend.png|290px|Legend for Colourmap]]
 
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== RC Extraction for C35/S35/H35 in IC 6.1 ==
 
== RC Extraction for C35/S35/H35 in IC 6.1 ==
  
 
To run RCX successfully, you must first pass LVS correctly as normal. Do this by running LVS without any switches. If you run RCX now, it will fail. Now carry out LVS with the switch "resimulate_extracted" to guarantee that also substrate shorts are found correctly. RCX will run without any problems (note that you must not use the "resimulate_extracted" switch for normal LVS runs as it may give false results.
 
To run RCX successfully, you must first pass LVS correctly as normal. Do this by running LVS without any switches. If you run RCX now, it will fail. Now carry out LVS with the switch "resimulate_extracted" to guarantee that also substrate shorts are found correctly. RCX will run without any problems (note that you must not use the "resimulate_extracted" switch for normal LVS runs as it may give false results.

Revision as of 17:31, 11 February 2009

Tips with their own pages

Vlsi:Cadence_Voltage_Storm

Virtual Connections in Assura LVS

If you have two wires on a layout that are unconnected but will be connected together in a higher level then place a pin on both wires. When running Assura LVS you need to set some further options. Enable "View avParameters" and then click "Modify avParameters...". Find the "joinPins" option, enable it ("Use in run") and set it to "Top". Click OK to close the avParameters window. Now enable "View Additional Functions" followed by "Use joinableNet Function". Now click "Modify joinableNet Function...". In the new window enable "root cell?" then add your net to the "Net Names to Join" box and click "Add to Command List (below)" to add it. Click OK to close the joinableNet window and then run LVS as normal.

Voltage / Current Pulse Sources

I can never remember which voltage/current is which, so I've created an image to remind me: Vpulse.png

RC Extraction for C35/S35/H35 in IC 6.1

To run RCX successfully, you must first pass LVS correctly as normal. Do this by running LVS without any switches. If you run RCX now, it will fail. Now carry out LVS with the switch "resimulate_extracted" to guarantee that also substrate shorts are found correctly. RCX will run without any problems (note that you must not use the "resimulate_extracted" switch for normal LVS runs as it may give false results.

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